Using GNU Make with cc65

Oliver Schmidt

2014-04-12
How to build your program using the GNU Make utility.

1. Overview

2. What is GNU Make?

3. A sample Makefile

4. Target-specific Variable Values


1. Overview

This document describes how to build your programs using the cc65 development tools and the GNU Make utility.

The cc65 development package doesn't come with a make utility. However this is no issue because GNU Make works very nicely with cc65.

2. What is GNU Make?

GNU Make is a both very powerful and very popular make utility. It might even be called the de facto standard for make utilities. For more information see the GNU Make home page:

http://www.gnu.org/software/make/

The cc65 development package is available as binaries for several host systems and can easily built for quite some additional systems. The very same is true for GNU Make so a cc65-based project coming with a GNU Make Makefile can easily be built by any cc65 developer no matter what host system is used.

Because of the strong alignment of the cc65 compiler with the ISO C standard it is very well feasible to compile a single C code base both with the cc65 compiler and other C compilers like for example GCC. GNU Make turns out to be very well suited to build projects for several target systems using multiple compilers as it isn't tied to any C compiler.

3. A sample Makefile

This Makefile is a fully functional sample for compiling several C sources (here foo.c and bar.c) and link the resulting object files into an executable program (here foobar):

SOURCES = foo.c bar.c

PROGRAM = foobar

ifdef CC65_TARGET
CC      = $(CC65_HOME)/bin/cl65
CFLAGS  = -t $(CC65_TARGET) --create-dep $(<:.c=.d) -O
LDFLAGS = -t $(CC65_TARGET) -m $(PROGRAM).map
else
CC      = gcc
CFLAGS  = -MMD -MP -O
LDFLAGS = -Wl,-Map,$(PROGRAM).map
endif

########################################

.SUFFIXES:
.PHONY: all clean
all: $(PROGRAM)

ifneq ($(MAKECMDGOALS),clean)
-include $(SOURCES:.c=.d)
endif

%.o: %.c
        $(CC) -c $(CFLAGS) -o $@ $<

$(PROGRAM): $(SOURCES:.c=.o)
        $(CC) $(LDFLAGS) -o $@ $^

clean:
        $(RM) $(SOURCES:.c=.o) $(SOURCES:.c=.d) $(PROGRAM) $(PROGRAM).map

Important: When using the sample Makefile above via copy & paste it is necessary to replace the eight spaces at the beginning of command lines (lines 26, 29 and 32) with a tab character (ASCII code 9).

3.1 Invoking the sample Makefile

Without any specific configuration the sample Makefile will compile and link using GCC. In order to rather use cc65 the variable CC65_TARGET needs to be defined. This may by done as an environment variable or simply as part of the Makefile. However to quickly switch between compilers and/or cc65 targets it is best done on the GNU Make command line like this:

make CC65_TARGET=c64

The sample Makefile presumes the variable CC65_HOME to point to the directory cc65 is located in. Again there are several ways to define this variable but as its value typically won't change often it is best done as an environment variable. On Windows the cc65 .exe installer package takes care of creating a CC65_HOME environment variable.

3.2 Understanding the sample Makefile

Most parts of the sample Makefile follow the guidelines in the GNU Make Manual that can be searched online for background information. The automatic generation of dependency however rather works as described by the GNU Make maintainer Paul D. Smith in "Advanced Auto-Dependencies". Fortunately both GCC and cc65 directly support this method in the meantime.

3.3 Invoking the sample Makefile on Windows

The recommended way to use GNU Make on Windows is to install it as part of a Cygwin environment. For more information see the Cygwin home page:

http://www.cygwin.com/

If however installing Cygwin shouldn't be an option for one or the other reason then the sample Makefile may be invoked from the Windows Command Prompt (cmd.exe) by downloading the following programs:

4. Target-specific Variable Values

The very limited resources of the cc65 target machines now and then require manual optimization of the build process by compiling individual source files with different compiler options. GNU Make offers Target-specific Variable Values perfectly suited for doing so. For example placing the code of the two modules foo and bar in the segment FOOBAR can be achieved with this target-specific variable definition:

foo.o bar.o: CFLAGS += --code-name FOOBAR